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Ordering number : ENA0167B
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Bi-CMOS IC
LV8054LP
Overview
For Digital Cameras
Single-chip motor Driver IC
LV8054LP is single-chip motor driver IC for digital cameras.
Functions
* Integrates the digital camera actuator drivers on a single chip * Four constant voltage output channels, two constant current output channels * All actuators can be driven at the same time * The AF and zoom stepping motors are driven by the clock signal * Supports PWM control of a DC zoom motor. * Can switch between an external input or an internal reference for the constant voltage output setting reference voltage * The constant voltage output multiplier can be set to one of 16 levels * The constant current output reference voltage can be set to one of 16 internal reference voltage levels * Built-in photosensor drive transistor * Three built-in Schmitt buffer circuits (the presence or absence of hysteresis can be set individually) Maximum Ratings at Ta = 25C
Parameter Supply voltage 1 Supply voltage 2 Peak output current Continuous output current Symbol VB max VCC max IO peak IO max1 IO max2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg OUT1 to 12 (t10mS, ON-duty20%) OUT1 to 12 PI Mounted on a circuit board* Conditions Ratings 6.0 6.0 600 400 85 1100 -20 to +85 -55 to +150 Unit V V mA mA mA mW C C
* Standard circuit board: 40x50x 0.8 mm3 glass epoxy four-layer board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
71807 MS / 20807 MS PC / 10606 MS OT 20051227-S00014 No.A0167-1/23
LV8054LP
Recommended Operating Conditions at Ta = 25C
Parameter Supply voltage range 1 Supply voltage range 2 Logic level input voltage Constant voltage setting input range Clock frequency PWM frequency FCLK FPWM CLK1, CLK2/PWM CLK2/PWM Symbol VB VCC VIN VC Conditions
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Ratings 2.7 to 5.5 2.7 to 5.5 0 to VCC+0.3 0.1 to VCC -64 -100
Unit V V V V KHz KHz
Electrical Characteristics at Ta = 25C, VB = 5V, VCC = 3.3V
Ratings Parameter Quiescent current Current drain 1 Current drain 2 VCC low-voltage cutoff voltage Low-voltage hysteresis Thermal shutdown temperature Thermal shutdown hysteresis Symbol ICCO IB ICC VthVCC VthHYS TSD TSD Design target value Design target value ST = low, BI1/2/3 = low ST = high, IN51/52/61/62 = low, BI1/2/3 = low, With no output load ST = high, IN51/52/61/62 = low, BI1/2/3 = low, With no output load 2.1 100 160 20 2.35 150 180 40 2.6 200 200 60 V mV C C 1.5 2.0 mA 500 Conditions min typ max 1 950 A A Unit
AF/Zoom Motor Drivers (OUT1/2, OUT3/4, OUT5/6, OUT7/8) Output on-resistance 1 Ronu1 Rond1 Output leakage current 1 Diode forward voltage 1 Internal reference voltage Constant voltage output IOleak1 VD1 VREF VOUT1 VOUT2 VC voltage divider voltage ratio VCR1 VCR2 VCR3 VCR4 VCR5 VCR6 VCR7 VCR8 VCR9 VCR10 VCR11 VCR12 VCR13 VCR14 VCR15 VCR16 VC = 0.88V VC = 0.88V (internal reference) (D3, D4, D5, D6) = (0, 0, 0, 0) (D3, D4, D5, D6) = (1, 0, 0, 0) (D3, D4, D5, D6) = (0, 1, 0, 0) (D3, D4, D5, D6) = (1, 1, 0, 0) (D3, D4, D5, D6) = (0, 0, 1, 0) (D3, D4, D5, D6) = (1, 0, 1, 0) (D3, D4, D5, D6) = (0, 1, 1, 0) (D3, D4, D5, D6) = (1, 1, 1, 0) (D3, D4, D5, D6) = (0, 0, 0, 1) (D3, D4, D5, D6) = (1, 0, 0, 1) (D3, D4, D5, D6) = (0, 1, 0, 1) (D3, D4, D5, D6) = (1, 1, 0, 1) (D3, D4, D5, D6) = (0, 0, 1, 1) (D3, D4, D5, D6) = (1, 0, 1, 1) (D3, D4, D5, D6) = (0, 1, 1, 1) (D3, D4, D5, D6) = (1, 1, 1, 1) ID = -400mA 0.7 0.84 4.2 4.2 95 92.8 90.7 88.5 86.4 84.2 82.0 79.9 77.7 75.6 73.4 71.2 69.1 66.9 64.8 62.6 0.9 0.88 4.4 4.4 100 97.7 95.5 93.2 90.9 88.6 86.4 84.1 81.8 79.5 77.3 75.0 72.7 70.5 68.2 65.9 Ta = 25C, IO = 200mA, High side on-resistance Ta = 25C, IO = 200mA, Low side on-resistance 0.7 0.5 0.85 0.65 1 1.2 0.92 4.6 4.6 105 102.6 100.2 97.8 95.5 93.1 90.7 88.3 85.9 83.5 81.1 78.7 76.4 74.0 71.6 69.2 A V V V V % % % % % % % % % % % % % % % %
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No. A0167-2/23
LV8054LP
Continued from preceding page.
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Ratings Parameter Logic pin input current Symbol IINL IINH High-level input voltage Low-level input voltage VINH VINL Conditions min VIN = 0V (ST, CLK1, CLK2/PWM) VIN = 3.3V (ST, CLK1, CLK2/PWM) ST, CLK1, CLK2/PWM ST, CLK1, CLK2/PWM 2.5 1.0 33 typ max 1.0 50 A A V V Unit
Shutter/AE Motor Drivers (OUT9-10, OUT11-12) Output on-resistance 2 Ronu2 Rond2 Output leakage current 2 Diode forward voltage 2 Constant current output Internal current setting reference voltages IOleak2 VD2 IO VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7 VREF8 VREF9 VREF10 VREF11 VREF12 VREF13 VREF14 VREF15 VREF16 Logic pin input current IINL IINH High-level input voltage Low-level input voltage VINH VINL ID = -400mA Rf = 1, (D3, D4, D5, D6) = (0, 0, 0, 0) (D3, D4, D5, D6) = (0, 0, 0, 0) (D3, D4, D5, D6) = (1, 0, 0, 0) (D3, D4, D5, D6) = (0, 1, 0, 0) (D3, D4, D5, D6) = (1, 1, 0, 0) (D3, D4, D5, D6) = (0, 0, 1, 0) (D3, D4, D5, D6) = (1, 0, 1, 0) (D3, D4, D5, D6) = (0, 1, 1, 0) (D3, D4, D5, D6) = (1, 1, 1, 0) (D3, D4, D5, D6) = (0, 0, 0, 1) (D3, D4, D5, D6) = (0, 0, 0, 1) (D3, D4, D5, D6) = (0, 1, 0, 1) (D3, D4, D5, D6) = (1, 1, 0, 1) (D3, D4, D5, D6) = (0, 0, 1, 1) (D3, D4, D5, D6) = (1, 0, 1, 1) (D3, D4, D5, D6) = (0, 1, 1, 1) (D3, D4, D5, D6) = (1, 1, 1, 1) VIN = 0V (IN51, IN52, IN61, IN62) VIN = 3.3V (IN51, IN52, IN61, IN62) IN51, IN52, IN61, IN62 IN51, IN52, IN61, IN62 2.5 1.0 33 0.7 190 0.190 0.162 0.157 0.152 0.147 0.143 0.138 0.133 0.128 0.124 0.119 0.114 0.109 0.105 0.100 0.095 0.9 200 0.200 0.170 0.165 0.160 0.155 0.150 0.145 0.140 0.135 0.130 0.125 0.120 0.115 0.110 0.105 0.100 Ta = 25C, IO = 200mA, High side on-resistance Ta = 25C, IO = 200mA, Low side on-resistance 0.7 0.5 0.85 0.65 1 1.2 210 0.210 0.179 0.173 0.168 0.163 0.158 0.152 0.147 0.142 0.137 0.131 0.126 0.121 0.116 0.110 0.105 1.0 50 A V mA V V V V V V V V V V V V V V V V A A V V
Photosensor peripheral circuits (PI, BI1, BO1, BI2, BO2, BI3, BO3) Output on-resistance 3 Output leakage current 3 Schmitt buffer threshold level (hysteresis) Schmitt buffer hysteresis Schmitt buffer threshold level (no hysteresis) Continued on next page. Ron3 IOleak3 VthH VthL Vthhys Vth 1.50 0.85 0.5 1.4 1.70 1.05 0.7 1.6 Ta=25C, IO= 60mA 2 2.5 1 1.90 1.25 0.9 1.8 A V V V V
No. A0167-3/23
LV8054LP
Continued from preceding page.
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Ratings Parameter Serial Data Transfer Pins Logic pin input current IINL IINH High-level input voltage Low-level input voltage Minimum SCLK high-level pulse width Minimum SCLK low-level pulse width Stipulated STB time Minimum STB pulse width Data setup time Data hold time Maximum CLK frequency Tlat Tlatw Tds Tdh Fclk 0.125 0.125 0.125 0.125 4 S S S S MHz Tscl 0.125 S VINH VINL Tsch VIN = 0V (SCLK, DATA, STB) VIN = 3.3V (SCLK, DATA, STB) SCLK, DATA, STB SCLK, DATA, STB 0.125 2.5 1.0 33 1.0 50 A A V V S Symbol Conditions min typ max Unit
Package Dimensions
unit : mm (typ) 3302A
Top View Bottom View
0.35 5.0 21 20 5.0 30 0.35 (0.7) 31
0.4
40 11 10 0.85MAX 0.2 1 (0.7)
0.05 0 NOM
SANYO : VQLP40(5.0X5.0)
No. A0167-4/23
LV8054LP
Block Diagram
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No. A0167-5/23
LV8054LP
Pin Functions
Pin No. 26 5 33 37 34 23 8 28 3 36 21 22 24 25 10 9 7 6 27 29 Symbol VB1 VB2 VB3 VB4 VCC PGND1 PGND2 RF1 RF2 SGND OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 Description Power supply for OUT1-4 Power supply for OUT5-8 Power supply for OUT9-10 Power supply for OUT11-12 Control system power supply Power system ground for OUT1-4 Power system ground for OUT5-8 Current detection connection for OUT9-10 Current detection connection for OUT11-12 Control system ground Motor driver output Motor driver output Motor driver output Motor driver output Motor driver output Motor driver output Motor driver output Motor driver output Motor driver output Motor driver output Pin No. 4 2 30 11 12 18 20 19 13 14 15 16 17 35 1 40 39 38 32 31 Symbol OUT11 OUT12 VC ST CLK1 SCLK DATA STB CLK2/PWM IN51 IN52 IN61 IN62 PI BI1 BO1 BI2 BO2 BI3 BO3
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Description Motor driver output Motor driver output External reference voltage input for the OUT1-8 constant current output Chip enable Stepping motor clock for OUT1-4 Serial data transfer clock Serial data Serial data latch pulse input Stepping motor clock/PWM signal input for OUT5-8 Control input for OUT9-10 Control input for OUT9-10 Control input for OUT11-12 Control input for OUT11-12 Photosensor drive output Schmitt buffer input 1 Schmitt buffer output 1 Schmitt buffer input 2 Schmitt buffer output 2 Schmitt buffer input 3 Schmitt buffer output 3
Pin Assignment
No. A0167-6/23
LV8054LP
Serial Data Input Overview
Serial Data Input Timing Chart
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Data is input in order from D0 to D7. Data is transferred on the SCLK rising edge and, after all data has been transferred, the data is latched by the rising edge of the STB signal. Note that the IC internal circuits will not accept the SCLK signal while the STB signal is high. Timing with which the Serial Data is Reflected in the Outputs Basically, the new values are reflected in the output at the point the data is latched with the STB signal. Pattern 1 However, the "Excitation direction" and "Excitation mode" settings used in stepping motor clock drive mode for channels 1 through 4 are an exception. In this case only, after the data is latched with the STB signal, the new values are reflected on the next rising edge of the CLK signal. Pattern 2
No. A0167-7/23
LV8054LP
Detailed Description of Serial Data Input
Note: This IC's channels are assigned as follows. OUT1/OUT2 Channel 1 OUT3/OUT4 Channel 2 OUT5/OUT6 Channel 3 OUT7/OUT8 Channel 4 OUT9/OUT10 Channel 5 OUT11/OUT12 Channel 6 Stepping motor excitation type for channels 1 through 4
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This IC supports connecting stepping motors to channels 1 and 2 and to channels 3 and 4. Either of these stepping motors can be controlled by a single clock signal. When this capability is used, the clock signal input pins and the channels as associated as shown below. CLK1: CLK2/PWM: Controls channel 1 and 2 drive. Controls channel 3 and 4 drive
The following state settings related to control of these stepping motors are set using the serial data. (See subsection, Serial Logic Table 1, in section ,Truth Tables, for a detailed description of this data.) * Excitation mode: * Excitation direction: * Step/Hold: * Counter reset: * Output enable: * VC voltage divisor: * VC voltage selection: 2-phase excitation or 1-2 phase excitation CW (clockwise) or CCW (counterclockwise) Clear or Hold Normal Operation or Reset Output Off or Output On Selects one of 16 values Internal or External
No. A0167-8/23
LV8054LP
Excitation Mode Setting This section presents the timing charts for each excitation mode. Two-Phase Excitation Timing Chart
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No. A0167-9/23
LV8054LP
1-2 Phase Excitation Timing Chart
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No. A0167-10/23
LV8054LP
Sample Timing Chart for the Excitation Direction Setting
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The excitation direction setting sets the excitation (rotation) direction of the stepping motor. With the CW (clockwise) setting, the phase of the channel 2 current is delayed from that of the channel 1 current by 90. With the CCW (counterclockwise) setting, the phase of the channel 2 current leads that of the channel 1 current by 90.
No. A0167-11/23
LV8054LP
Step/Hold Operation Overview
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Sample Timing Chart for the Step/Hold Setting When the Step/Hold data is set to the Hold state, the state of the external clock signal (CLK) at that time is latched and held as the internal clock signal. At the timing with which Step/Hold is set to the Hold state for the first time in the figure below, the internal clock signal will be held at the low level because the external clock (CLK) was at the low level. In contrast, at the timing with which Step/Hold is set to the Hold state for the second time, the internal clock signal will be held at the high level because the external clock (CLK) was at the high level. When Step/Hold is set to the Clear state, the internal clock is synchronized with the external clock (CLK). The output holds the state it was in at the point Step/Hold is set to the Hold state, and advances on the next clock signal rising edge after Step/Hold is set to the Clear state. As long as Step/Hold is in the Hold state, the position number does not advance even if an external clock (CLK) signal is applied.
No. A0167-12/23
LV8054LP
Sample Timing Chart for the Counter Reset Setting
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When the Counter Reset setting is set to the Reset state, the output goes to the initial state on the rising edge of the STB signal. Then, when the Counter Reset setting is set to the Normal Operation (cleared) state, the output begins to advance the position number on the rising edge of the CLK signal following the rise of the STB signal.
Sample Timing Chart for the Output Enable Setting When the Output Enable setting is set to the Output Off state, the outputs are turned off and set to the high-impedance state on the rising edge of the STB signal. Note, however, that since the internal clock continues to operate, the position number advances as long as a clock signal (CLK) is input. Therefore, when the Output Enable setting is next set to the Output On (cleared) state, the output is turned on at the STB signal rising edge and the output levels at that time will be those for the position number to which the state has advanced due to the CLK signal input.
No. A0167-13/23
LV8054LP
DC Motor and Voice Coil Motor Drive Methods (Channels 3 and 4)
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When channels 3 and 4 are used to drive a DC or voice coil motor, the drive polarity is set with the serial data. The procedure for setting the drive polarity is shown below. (See subsection, Serial Logic Table 2, in section, Truth Tables, for a detailed description of this data.) Setting Procedure (1) Select PWM signal input with the CLK2/PWM selection item in the serial data. This sets up the signal input to the CLK2/PWM pin to be accepted as a PWM signal for channel 3 or channel 4. (In this case, it is not used as a clock signal.) (2) If the output is to be controlled by PWM control, set up PWM mode and PWM signal allocation with the serial data. (3) Set the drive polarity for each channel with the serial data. (4) If the output is to be controlled by PWM control, input the PWM signal to the CLK2/PWM pin. The following tables describe the correspondence between the PWM signal and the output logic. Operation in Slow Decay Mode (forward/reverse brake)
Serial input D4 0 1 0 1 D5 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 H 0 0 1 1 OFF L L L OFF L L L OFF L L L OFF L L L L D6 D7 PWM input CLK2/PWM OUT5 OFF H L L OUT6 OFF L H L OFF H L L OFF L H L Output OUT7 OUT8 Standby mode OUT5 OUT6 OUT6 OUT5 Brake mode Standby mode OUT7 OUT8 OUT8 OUT7 Brake mode Standby mode Brake mode Brake mode Brake mode Standby mode Brake mode Brake mode Brake mode Mode
No. A0167-14/23
LV8054LP
Operation in Fast Decay Mode (forward/reverse standby mode)
Serial input D4 0 1 0 1 D5 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 H 0 0 1 1 OFF OFF OFF L OFF OFF OFF L OFF OFF OFF L OFF OFF OFF L L D6 D7 PWM input CLK2/PWM OUT5 OFF H L L OUT6 OFF L H L OFF H L L OFF L H L Output OUT7 OUT8
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Mode Standby mode OUT5 OUT6 OUT6 OUT5 Brake mode Standby mode OUT7 OUT8 OUT8 OUT7 Brake mode Standby mode Standby mode Standby mode Brake mode Standby mode Standby mode Standby mode Brake mode
Constant Voltage Control Setup Procedure for Channels 1 to 4 The constant voltage set value for channels 1 to 4 can be set separately for channels 1 and 2 and for channels 3 and 4. (See subsections, Serial Logic Table 3, and, Serial Logic Table 4, in section, Truth Tables, for a detailed description of this data.) The reference voltage used as the basis for operation can be selected to be either the internal reference voltage (0.88V) or the external input voltage (the voltage applied to the VC pin). The reference voltage selected as described above is voltage divided by the ratio set by the VC voltage divisor set by the serial data. The result of that voltage division operation is multiplied by five by the output constant voltage circuit and then output. The following formulas can be used to calculate the output constant voltage for the individual cases. When the internal reference voltage is used: (output constant voltage) = (internal reference voltage (0.88 V)) x (VC voltage divisor) x 5 When the external reference voltage (VC input voltage) is used: (output constant voltage) = (VC input voltage) x (VC voltage divisor) x 5
No. A0167-15/23
LV8054LP
Voice Coil Motor and Stepping Motor Drive Methods (Channels 5 and 6)
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When channel 5 or 6 is used to drive either a voice coil motor or stepping motor, the drive polarity can be set with either serial data or parallel data (the IN51, IN52, IN61, and IN62 input signals). This section describes the procedures used for these settings. (See subsection, Serial Logic Table 2, in section, Truth Tables, for a detailed description of this data.) Setting Procedure Using Serial Data A: Channel 5 1. Set the IN51 and IN52 pins to the low level. (Alternative, they may be left open.) 2. Set the drive polarity with the serial data B: Channel 6 1. Set the IN61 and IN62 pins to the low level. (Alternative, they may be left open.) 2. Set the drive polarity with the serial data Setting Procedure Using Parallel Data The IN51 and IN52 pins are used to set the channel 5 drive polarity and the IN61 and IN62 pins are used to set the channel 6 drive polarity. The truth table for this function is shown below.
Parallel inputs IN51 L L H H IN52 L H L H L L H H L H L H IN61 IN62 OUT9 L L H L OUT10 L H L L L L H L L H L L Outputs OUT11 OUT12 Standby mode OUT10 OUT9 OUT9 OUT10 Brake Standby mode OUT12 OUT11 OUT11 OUT12 Brake Parallel priority Serial priority Parallel priority Serial priority Mode
Constant Current Control Settings (channels 5 and 6) The constant current settings for channels 5 and 6 are set individually for each channel. (See subsection, Serial Logic Table 5, in section, Truth Tables, for a detailed description of this data.) The output constant current is set by the constant current reference voltage set with the serial data and the resistor (RF) connected between the RF1 and RF2 pins. The following formula can be used to calculate the output constant current. (output constant current) = (constant current reference voltage) / (value of the resistor RF) PI Output Drive Method When the PI output is used to drive a photosensor, the drive on/off state is set from the serial data. (See subsection, Serial Logic Table 5, in section, Truth Tables, for a detailed description of this data.) Schmitt Buffer Hysteresis Setting The presence or absence of hysteresis in the BO1, BO2, and BO3 Schmitt buffer outputs can be set individually with the serial data. (See subsection, Serial Logic Table 5, in section, Truth Tables, for a detailed description of this data.)
No. A0167-16/23
LV8054LP
Truth Tables
Serial Logic Table 1
Input D0 D1 D2 D3 0 1 * * 0 0 0 * * * * * * 0 1 * * 1 0 0 * * * * * * D4 * * 0 1 * * * * * * * * 0 1 * * * * * * D5 * * * * 0 1 * * * * * * * * 0 1 * * * * D6 * * * * * * 0 1 * * * * * * * * 0 1 * * D7 * * * * * * * * 0 1 * * * * * * * * 0 1 AF Counter Reset AF Output Enable Zoom Excitation Direction Zoom Excitation Mode Zoom Step/Hold Zoom Counter Reset Zoom Output Enable AF Excitation Direction AF Excitation mode AF Step/Hold CW (clockwise) CCW (counterclockwise) 2-phase excitation 1-2 phase excitation Clear Hold Reset Clear Output Off Output On CW (clockwise) CCW (counterclockwise) 2-phase excitation 1-2 phase excitation Clear Hold Reset Clear Output Off Output On Setting mode Content set Notes Channels set 1ch 2ch 3ch 4ch 5ch 6ch
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Serial data PI activation timing CLK1 CLK2 STB
No. A0167-17/23
LV8054LP
Serial Logic Table 2
Input Setting mode D0 D1 D2 D3 D4 0 1 0 0 1 * * * 0 1 0 * 0 1 0 1 1 * * * * 0 1 * * * 0 D5 0 0 1 1 * * * * 0 0 1 1 * * * * * * * D6 * * * * 0 1 0 1 * * * * 0 1 0 1 * * * D7 * * * * 0 0 1 1 * * * * 0 0 1 1 * * * PWM mode * 1 1 0 * * * * * * 1 * * * * * * * 0 1 0 1 * * * 0 0 1 1 * * * * * * * 0 1 (Dummy data) PWM signal allocation CLK2/PWM selection OUT11-12 drive polarity (6ch) OU9-10 drive polarity (5ch) OUT7-8 drive polarity (4ch) OUT5-6 drive polarity (3ch) OFF OUT5 OUT6 OUT6 OUT5 Brake OFF OUT7 OUT8 OUT8 OUT7 Brake OFF OUT9 OUT10 OUT10 OUT9 Brake OFF OUT11 OUT12 OUT12 OUT11 Brake CLK2 signal input *4 PWM signal input Slow Decay (Forward/reverse brake) Fast Decay (Forward/reverse standby mode) OFF Channel 3 only Channel 4 only Both channels 3 and 4 *3 *2 *1 *1 Content set Notes 1ch 2ch 3ch 4ch 5ch 6ch Channels set
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Serial data PI activation timing CLK1 CLK2 STB
*5
*6
No. A0167-18/23
LV8054LP
Serial Logic Table 3
Input D0 D1 D2 D3 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 * * D4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * * D5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * * D6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * * D7 * * * * * * * * * * * * * * * * 0 1 VC voltage selection VC voltage divisor (The values in parentheses indicate the output voltage value when the internal reference voltage (0.88V) is used.) 100% (4.4V) 97.7% (4.3V) 95.5% (4.2V) 93.2% (4.1V) 90.9% (4.0V) 88.6% (3.9V) 86.4% (3.8V) 84.1% (3.7V) 81.8% (3.6V) 79.5% (3.5V) 77.3% (3.4V) 75.0% (3.3V) 72.7% (3.2V) 70.5% (3.1V) 68.2% (3.0V) 65.9% (2.9V) Internal reference voltage (0.88V) VC input voltage *7 Setting mode Content set Notes Channels set 1ch 2ch 3ch 4ch 5ch 6ch
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Serial data PI activation timing CLK1 CLK2 STB
Serial Logic Table 4
Input D0 D1 D2 D3 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 * * D4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * * D5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * * D6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * * D7 * * * * * * * * * * * * * * * * 0 1 VC voltage selection VC voltage Divisor (The values in parentheses indicate the output voltage value when the internal reference voltage (0.88V) is used.) 100% (4.4V) 97.7% (4.3V) 95.5% (4.2V) 93.2% (4.1V) 90.9% (4.0V) 88.6% (3.9V) 86.4% (3.8V) 84.1% (3.7V) 81.8% (3.6V) 79.5% (3.5V) 77.3% (3.4V) 75.0% (3.3V) 72.7% (3.2V) 70.5% (3.1V) 68.2% (3.0V) 65.9% (2.9V) Internal reference voltage (0.88V) VC input voltage *7 Setting mode Content set Notes Channels set 1ch 2ch 3ch 4ch 5ch 6ch Serial data PI activation timing CLK1 CLK2 STB
No. A0167-19/23
LV8054LP
Serial Logic Table 5
Input D0 D1 D2 D3 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 * * 0 1 * * * 1 1 1 * * * * * * * * * * 1 * * * * * 0 1 * * * * * 0 1 D4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * * * * 0 1 * D5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * * * * * * 0 D6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * * * * * * * D7 * * * * * * * * * * * * * * * * 0 1 * * * * * Channel selection Photosensor drive Buffer output hysteresis (BI1/BO1) Buffer output hysteresis (BI2/BO2) Buffer output hysteresis (BI3/BO3) (Dummy data) Constant current reference voltage 0.200V 0.170V 0.165V 0.160V 0.155V 0.150V 0.145V 0.140V 0.135V 0.130V 0.125V 0.120V 0.115V 0.110V 0.105V 0.100V OUT9-10 (5ch) OUT11-12 (6ch) OFF ON Absent Present Absent Present Absent Present Setting mode Content set Notes Channels set 1ch 2ch 3ch 4ch 5ch 6ch
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Serial data PI activation timing CLK1 CLK2 STB
Notes *1. The operating mode can be switched between forward (or reverse) brake mode and forward (or reverse) standby mode operation with the CLK2/PWM pin in combination with notes 5 and 6 below. *2. These serial inputs are only accepted when the parallel inputs IN51 and IN52 are both at the low level. In all other states, the serial input will be ignored. *3. These serial inputs are only accepted when the parallel inputs IN61 and IN62 are both at the low level. In all other states, the serial input will be ignored. *4. Selects whether the CLK2/PWM input functions as a stepping motor clock (CLK2) or a DC motor PWM signal (PWM). *5. Forcibly switches the logic of note 1 to brake mode when the CLK2/PWM input is high. *6. Forcibly switches the logic of note 1 to standby mode when the CLK2/PWM input is high. *7. Voltage divisor for the VC voltage divider circuit. After either the VC input voltage or the internal reference voltage is voltage divided by this ratio, the result of that division is multiplied by five by the output constant voltage circuit.
No. A0167-20/23
LV8054LP
Pin Internal Equivalent Circuits
Pin No. 1 39 32 Symbol BI1 BI2 BI3 Equivalent circuit
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4 2 3
OUT11 OUT12 RF2
27 29 28
OUT9 OUT10 RF1
10 9 7 6
OUT5 OUT6 OUT7 OUT8
Continued on next page.
No.A0167-21/23
LV8054LP
Continued from preceding page. Pin No. 21 22 24 25 Symbol OUT1 OUT2 OUT3 OUT4 Equivalent circuit
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11 12 13 14 15 16 17 18 19 20
ST CLK1 CLK2/PWM IN51 IN52 IN61 IN62 SCLK STB DATA
30
VC
40 38 31
BO1 BO2 BO3
35
PI
No.A0167-22/23
LV8054LP
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SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of July, 2007. Specifications and information herein are subject to change without notice. PS No.A0167-23/23

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